1. Field of the Invention
The present invention relates to an address generating circuit for data compression which functions to read out data stored in a defect analyzing memory into a CPU with any desired compression ratio at a high speed.
2. Prior Art
According to the conventional technique data for all addresses stored in an error analyzing memory are read out into a CPU and thereafter they are converted into a corresponding compression ratio with help of a software.
The problem to be solved by the present invention As the conventional technique converts data using software, a long period of time is required not only for taking in all data but also for processing the data.